Logic Circuits Utilizing Combinational MOS

Combinational logic circuits, also known as gates, execute Boolean operations on multiple input variables and generate outputs as Boolean functions of the inputs. These circuits are fundamental components of digital systems. While a combinational circuit exclusively relies on input variables to produce an output, a sequential circuit considers both the current input and previous output variables to generate its output.

A multiplexer is a combinational circuit with multiple data inputs and a single output, which is determined by control or select inputs. For N input lines, there are log n (base 2) selection lines required, or we can say that for 2^n input lines, n selection lines are needed. Multiplexers are also referred to as “Data n selector, parallel to serial converter, many to one circuit, universal logic circuit”. Their main purpose is to enhance the capacity of data transmission over a network within a specific timeframe and bandwidth.

Presented here is the utilization of truth table and gates to implement a 4:1 Multiplexer.

A multiplexer has the ability to function as a universal combinational circuit, capable of implementing all standard logic gates.

a) Utilizing a 2:1 multiplexer to implement a NOT gate.


NOT Gate :

An analysis can be conducted on the equation Y = x’.1 + x.0 = x’, which represents a NOT Gate implemented using a 2:1 MUX. The implementation of a NOT gate requires “n” selection lines and cannot be achieved with “n-1” selection lines. It is important to note that only a NOT gate cannot be implemented using “n-1” selection lines.

b) Utilizing a 2:1 Mux to implement an AND gate.


AND GATE

The utilization of “n-1” selection lines is employed in this implementation.
“””.

c) Utilizing a 2:1 Mux to implement an OR gate.

ng “n-1” selection lines.


OR GATE

To implement NAND, NOR, XOR, and XNOR gates, two 2:1 multiplexers are needed. The first multiplexer serves as a NOT gate, supplying the inverted input to the second multiplexer.

Implementation of a 2:1 Mux can be used to create a NAND gate.


NAND GATE


e) Implement

n of NOR gate using 2 : 1 Mux


NOR GATE

f) The 2:1 Mux can be utilized to implement an EX-OR gate.


EX-OR GATE

g) Utilizing a 2:1 Mux to implement an EX-NOR gate.


EX-NOR GATE

Utilizing lower order MUX to implement a higher order MUX.

a) Implement a 4:1 multiplexer using a combination of two 2:1 multiplexers.

To implement a 4:1 MUX, three 2:1 MUXes are necessary.

Similarly,

The requirement for a 8:1 MUX is the same as that of a 2:1 MUX. Similarly, the requirement for a 16:1 MUX is the same as that of a 2:1 MUX multiplied by 15, and the requirement for a 64:1 MUX is the same as that of a 2:1 MUX multiplied by 63. Therefore, we can conclude that a 2^n:1 MUX requires (2^n – 2) 2:1 MUXes.

Implementing a 16:1 multiplexer by utilizing a 4:1 multiplexer.

Typically, when implementing a B:1 MUX with an A:1 MUX, a single formula is used for the implementation. This formula involves dividing B by A to obtain K1, dividing K1 by A to obtain K2, and dividing K2 by A to obtain K3.

………………

For each count of MUX obtained, A is equal to K divided by N-1, where N is equal to 1.

The sum of all the numbers of MUXes, denoted as K1 + K2 + K3 + … + K_N, should be calculated. For instance, if we want to implement a 64:1 MUX using a 4:1 MUX, we can use the above formula to determine the number of MUXes needed. By dividing 64 by 4, then 16 by 4, and finally 4 by 4 until we reach a count of 1 MUX, we find that a total of 21 4:1 MUXes are required for the implementation of the 64:1 MUX.

To implement a boolean function using a MUX, we can use minimal and don’t care terms as inputs. For example, let’s consider the boolean function f(A, B, C) = Σ(1, 2, 3, 5, 6) with a don’t care term (7). We can use a 4:1 MUX with AB as the select input. By expanding the minterms to their boolean form, we can determine their 0 or 1 value in the Cth place and arrange them accordingly.

c) Selecting BC
: By expanding the minterms to their boolean form, we can determine their 0 or 1 value in A’s position, allowing us to arrange them accordingly.

The author of this article is Sumouli Choudhury.

Frequently Asked Questions

Posted in Uncategorized